1. Field of the Invention
The present invention relates to output buffer circuits and, more specifically, to techniques for reducing an output delay in slew-rate controlled output buffer circuits.
2. Description of the Background Art
Conventionally, an output buffer circuit includes a driver circuit that outputs a driver signal from an output node between a PMOS transistor for output and an NMOS transistor for output, a driver control circuit that controls the gates of the PMOS transistor for output and the NMOS transistor for output based on a supplied control signal, and a capacitor circuit that is interposed between the driver circuit and the driver control circuit, and controls a slew rate by using a capacitor.
The slew rate of an output buffer circuit is defined by such standards as ATA/ATAPI, and strobe signal and data having a period of 30 nanoseconds are defined by such protocols as UltraDMA-mode 6. For this reason, there has been a demand for an output buffer circuit having an accurately controlled slew rate with little delay.
In conventional output buffer circuits, the driver signal output from the output node between the PMOS transistor for output and the NMOS transistor for output is returned to the gates of the PMOS transistor for output and the NMOS transistor for output via the capacitor, to thereby set a prescribed slew rate.
In the conventional output buffer circuits, however, the gates of the PMOS transistor for output and the NMOS transistor for output are controlled only via a constant current source that is included in the driver control circuit. The operation of the constant current source therefore takes time, sometimes causing an increase in delay.
National Publication of Translation No. 2001-508635 discloses, as shown in FIG. 6, reducing a delay by connecting a capacitor CF returned from an output node vo alternately to the gate of a PMOS transistor P1 for output and the gate of an NMOS transistor N1 for output.
In National Publication of Translation No. 2001-508635, the capacitor CF to be connected to the gates is expected to have a potential of (gate potential of the NMOS transistor N1 for output (power supply potential)−NMOS threshold voltage Vthn) prior to being connected to the gate of the PMOS transistor P1 for output. But when a control signal input to an input node vi remains at an L level for a long time due to an intermission and the like, the potential of the capacitor CF does not become the (gate potential of the NMOS transistor N1 for output (power supply potential)−NMOS threshold voltage Vthn) due to leakage of the transistors and the like. Namely, the potential of the capacitor CF becomes a gate potential of the NMOS transistor N1 for output (power supply potential), resulting in little delay reduction.
Likewise, in National Publication of Translation No. 2001-508635, the capacitor CF to be connected to the gates is expected to have a potential of (gate potential of the PMOS transistor P1 for output (ground potential)+PMOS threshold voltage Vthp) prior to being connected to the gate of the NMOS transistor N1 for output. But when a control signal input to the input node vi remains at an H level for a long time due to an intermission and the like, the potential of the capacitor CF becomes the gate potential of the PMOS transistor P1 for output (ground potential) due to leakage of the transistors and the like, resulting in little delay reduction. In addition, the signals having a long “L” period and a long “H” period input to the input node vi cause a change in output delay.